The speed that a memory can be accessed either for writing or reading is critical to many electronic applications. Memory speed can be increased by increasing the clock speed of the memory system which, in the case of a multi-stage pipelined synchronous memory, generally translates to improving the actual memory array access cycle, called “array cycle” throughout the rest of the document. The array cycle is usually the limiting factor in increasing the memory's speed, even when multiple pipeline stages are used. Increasing the memory speed results in tighter internal operation windows, which in turn increase the likelihood of race conditions that often cause write/read failures. Limited efforts have been made to decrease the array cycle time for memories. There have been efforts to first predocode the address and then latch or register the predecoded address. However, these efforts do not comprehensively process the external address before decoding the internal address signal. They only capture the full external address and do not take into account counter control signals that determine the information stored in the counter, mask, mirror, and read-back latches/registers. In addition, the prior art does not have internal enable control signals—generated in the counter block—that control either the array address, the array read/write, or the activation/deactivation (i.e., the high/low impedance state) of the data and/or address outputs.
Thus, there exists a need for a synchronous memory with a shadow-cycle counter that improves memory cycle time and provides other important memory control capabilities.